Lecture notes(disabled):

Module 1

Module 2

Module 3

Module 4

Lab 1

Module 5

Module 6

Module 7

Lab 2

Module 8

Module 9

Module 10

Module 11

Schedule

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Schedule for Intel instructors

 

Date	Module	Instructors	Time	Venue
9th Aug 2004	4. IC Design Flow and Layout	KWLoh	2-4pm	Makmal Intel (Jabatan Kejuruteraan Electrik)
16th Aug 2004	Lab 1/Home Work	Hong Kiat/KW Loh	2-6pm	Makmal Intel (JKE)
23rd Aug 2004	6&7. Layout Hierarchy/Advance Hierarchy Concept + Submit Lab1 Home Work	Willetts/Jason Au	2-6pm	Makmal Intel (JKE)
30th Aug 2004	5. Layout Quality + Review Lab1 Home Work	LK Ng	2-6pm	Makmal Intel (JKE)
6th Sept 2004	Lab 2.1. Complete PR19. Home Work: PR20 & 21.	Hong Kiat/Jessica	2-6pm	Makmal Intel (JKE)
13th Sept 2004	Holiday
20th Sept 2004	Holiday
27th Sept 2004	Lab 2.2. Array + Decoder	Hong Kiat/Jessica	2-6pm	Makmal Intel (JKE)
4th Oct 2004	Lab 2.3. Continue EXRAM	Hong Kiat/Jessica	2-6pm	Makmal Intel (JKE)
11th Oct 2004	8. Auto Place & Route + Submit EXRAM Home Work	Hun Wah	2-4pm	Makmal Intel (JKE)
18th Oct 2004	9. ESD and Latch Up	Hun Wah	2-4pm	Makmal Intel (JKE)
25th Oct 2004	10. Full Chip Integration	KC Foong	2-4pm	Makmal Intel (JKE)
1st Nov 2004	11. Tape Out + PDC Visit	KC Foong/EG Tan	PDC Visit	Penang Design Center

Contact Person:

PUO           Cik Noorolpadzilah Bt Mohd Zan (Primary)  HP: 012-

                 Email: nrol@jke.puo.edu.my or l@yahoo.com

PUO           Mr. Chua Keow  HP: 017

                 Email: h@jke.puo.edu.my

PUO            Ir Chan Loong

                  Email: c@jke.puo.edu.my

                  Tel: 605-54576/54622/54560  Ext:1241

                  Penolong KJ - Pn. Hamimah Ext: 1210

Intel           Law Liang Ming

Maps:

From South Exit of Ipoh to PUO

PUO Campus

Useful Links:

Polytechnic Ungku Omar

Intel

Tanner (L-edit developer)

Any issue please email Law, Liang Ming